Block Diagram 8259A
The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for use with the 8085 and 8086 microprocessors.
The 8259 can be used for applications that use more than five numbers of interrupts from multiple sources.
The main features of 8259 are listed below
- Manage eight levels of interrupts.
- Eight interrupts are spaced at the interval of four or eight locations.
- Also, Resolve eight levels of priority in fully nested mode, automatic rotation mode or specific rotation mode.
- Mask each interrupt individually.
- Moreover, Read the status of the pending interrupt, in-service interrupt, and masked interrupt.
- Accept either the level triggered or edge triggered interrupt
8259 Internal Block Diagram
- It is typical R/W logic.
- Also, When address line A0 is at logic 0, the controller selected to write a command word or read status.
- The Chip Select logic and A0 determine the port address of the controller.
- It has two pins: INT as output and INTA as input.
- Also, The INT connected to INTR pin of MPU
Interrupt Registers and Priority Resolver
- Interrupt Request Register (IRR)
- also, Interrupt In-Service Register ( ISR )
- Priority Resolver
- Moreover, Interrupt Mask Register (IMR)
Interrupt Request Register (IRR) and Interrupt In-Service Register (ISR)
- Moreover, Interrupt input lines handled by two registers in cascade – IRR, and ISR
- Also, IRR used to store all interrupt which requesting service.
- ISR used to store all interrupts which serviced.
- This logic block determines the priorities of the bit set in IRR.
- Also, IR0 is having highest priority, IR7 is having lowest priority
Interrupt Mask Register
- It stores bits which mask the interrupt lines to masked
- IMR operates on the IRR.
- Moreover, Masking of high priority input will not affect the interrupt request lines.
Cascade Buffer / Comparator
- This block used to expand the number of interrupt levels by cascading two or more 8259 As.
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