Parallel Arbitration Logic
- The parallel bus arbitration technique uses an external priority encoder and a decoder as shown in the figure.
- Each bus arbiter in the parallel scheme has a bus request output line and a bus acknowledge input line.
- Each arbiter enables the request line when its processor is requesting access to the system bus.
Figure: Parallel arbitration
- The processor takes control of the bus if it acknowledges input line enabled.
- The bus busy line provides an orderly transfer of control, as in the Daisy chaining case.
- Generally, The figure shows the request lines from four arbiters going into a 4 X 2 priority encoder.
- The output of the encoder generates a 2-bit code which represents the highest-priority unit among those requesting the bus.
- The bus priority-in (BPRN) and bus priority-out (BPRO used for a daisy-chain connection of bus arbitration circuits.
- Also, The bus busy signal BUSY an open-collector output used to instruct all arbiters when the bus is busy conducting a transfer.
- The common bus request (CBRQ) is also an open-collector output that serves to instruct the arbiter if there are any other arbiters of lower-priority requesting use of the system bus.
- Moreover, The signals used to construct a parallel arbitration procedure are bus request (BREQ) and priority-in (BPRN), corresponding to the request and acknowledgment signals in the figure.
- The bus clock (BCLK) used to synchronize all bus transactions.