- The internal architecture of the 80386 includes six functional units that operate in parallel. The parallel operation is called as pipeline processing.
- Moreover, Fetching, decoding execution, memory management, and bus access for several instructions are performed simultaneously.
- Also, The six functional units of the 80386 Architecture are
- Bus Interface Unit
- Code Pre-fetch Unit
- Instruction Decoder Unit
- Execution Unit
- Segmentation Unit
- Paging Unit
- The Bus Interface Unit connects the 80386 with memory and I/O. Based on internal requests for fetching instructions and transferring data from the code pre-fetch unit, the 80386 Architecture generates the address, data and control signals for the current bus cycles.
- Also, The code pre-fetch unit pre-fetches instructions when the bus interface unit is not executing the bus cycles. It then stores them in a 16-byte instruction queue for decoding by the instruction decode unit.
- Moreover, The instruction decode unit translates instructions from the pre-fetch queue into microcodes. The decoded instructions then stored in an instruction queue (FIFO) for processing by the execution unit.
The execution unit processes the instructions from the instruction queue. It contains a control unit, a data unit and a protection test unit.
- The control unit contains microcode and parallel hardware for fast multiply, divide, and effective address calculation. The unit includes a 32-bit ALU, 8 general purpose registers and a 64-bit barrel shifter for performing multiple bit shifts in one clock. The data unit carries out data operations requested by the control unit.
- Moreover, The protection test unit checks for segmentation violations under the control of microcode.
- Also, The segmentation unit calculates and translates the logical address into linear addresses at the request of the execution unit.
- The translated linear address sent to the paging unit. Upon enabling the paging mechanism, the 80386 translates these linear addresses into physical addresses.
- Also, If paging not enabled, the physical address is identical to the linear address and no translation is necessary.