Block Diagram (8255A): Programmable Peripheral Interface
Read Write Control Logic
- This is an active low signal that enables the Read operation. When signal is low MPU reads data from selected I/O port of 8255A
- Also, This is an active low signal that enables Write operation. When signal is low MPU writes data into selected I/O port or control register
- Also, This is an active high signal, used to reset the device. That means clear control registers
- This is an Active Low signal. When it is low, then data is transfer from 8085
- CS signal is the master Chip Select.
- A0 and A1 specify one of the I/O ports or control register
Data Bus Buffer
- This three-state bi-directional 8-bit buffer used to interface the 8255 to the system data bus.
- Data transmitted or received by the buffer upon execution of input or output instructions by the CPU.
- Control words and status information also transferred through the data bus buffer.
Group A and Group B Controls
- The functional configuration of each port programmed by the systems software. In essence, the CPU “outputs” a control word to the 8255.
- The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the 8255.
- Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports.
Ports A, B, and C
- The 8255 contains three 8-bit ports (A, B, and C).
- Moreover, All can configure to a wide variety of functional characteristics by the system software but each has its own special features or “personality” to further enhance the power and flexibility of the 8255.
- Port A One 8-bit data output latch/buffer and one 8-bit data input latch.
- Both “pull-up” and “pull-down” bus-hold devices are present on Port A.
- Also, Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
- Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can divide into two 4-bit ports under the mode control.
- Also, Each 4-bit port contains a 4-bit latch and it can use for the control signal output and status signal inputs in conjunction with ports A and B.