Cache Coherence Problem Solution
Various schemes have been proposed to solve the cache coherence problem in shared memory multiprocessors.
Disallow private caches
- A simple scheme is to disallow private caches for each processor and have a shared cache memory associated with main memory.
- Moreover, Every data access is made to the shared cache.
- Also, This method violates the principle of the closeness of CPU to cache and increases the average memory access time.
- In effect, this scheme solves the problem by avoiding it.
Read-Only Data are Cacheable
- The scheme that allows only nonshared and read-only data to be stored in caches. Such items called cachable.
- Shared writable data are noncacheable.
- The compiler must tag data as either cachable or noncacheable, and the system hardware makes sure that only cachable data stored in caches.
- Also, The noncacheable data remain in main memory.
- This method restricts the type of data stored in caches and introduces an extra software overhead that may degrade performance.
Centralized Global Table
- A scheme that allows writable data to exist in at least one cache is a method that employs a centralized global table in it compiler.
- Moreover, The status of memory blocks stored in the central global table.
- Each block identified as read-only (RO) or reads and write (RW).
- All caches can have copies of blocks identified as RO.
- Also, Only one cache can have a copy of an RW block.
- Thus if the data updated in the cache with an RW block, the other caches not affected because they do not have a copy of this block.
Hardware-only solutions handled by the hardware automatically and have the advantage of higher speed and program transparency.
Snoopy Cache Controller
- In the hardware solution, the cache controller specially designed to allow it to monitor all bus requests from CPUs and IOPs.
- All caches attached to the bus constantly monitor the network for possible write operations.
- Also, Depending on the method used, they must then either update or invalidate their own cache copies when a match detected.
- The bus controller that monitors this action referred to as a snoopy cache controller.
- So, This basically a hardware unit designed to maintain a bus-watching mechanism over all the caches attached to the bus.
- All the snoopy controllers watch the bus for memory store operations.
- When a word in a cache updated by writing into it, the corresponding location in main memory also updated.
- Moreover, The local snoopy controllers in all other caches check their memory to determine if they have a copy of the word that has overwritten.
- If a copy exists in a remote cache, that location marked invalid.
- Also, Because all caches snoop on all bus writes, whenever a word is written, the net effect is to update it in the original cache and main memory and remove it from all other caches.
- If at some future time a processor accesses the invalid item from its cache, the response equivalent to a cache miss. And the updated item transferred from main memory. In this way, inconsistent versions prevented.