Cache coherence problem
- To ensure the ability of the system to execute memory operations correctly, the multiple copies must keep identical.
- This requirement imposes a cache coherence problem.
- Moreover, A memory scheme is coherent if the value returned on a load instruction always the value given by the latest store instruction with the same address.
- Cache coherence problems exist in multiprocessors with private caches because of the need to share writable data.
- Read-only data can safely replicate without cache coherence enforcement mechanisms. To illustrate the problem, consider the three-processor configuration with private caches shown in the figure.
- Also, During the operation, an element X from main memory loaded into the three processors, P1, P2, and P3.
- It is also copied into the private caches of the three processors.
- Also, For simplicity, we assume that X= 52.
- The load on X to the three processors results in consistent copies in the caches and main memory.
- Moreover, If one of the processors performs a store to X, the copies of X in the caches become inconsistent.
- A load by the other processors will not return the latest value.
Figure: Cache configuration after a store to X by processor P1
- As shown in the figure, a store X (of the value of 120) into the cache of processor P1 updates memory to the new value in a write-through policy.
- A write-through policy maintains consistency between memory and the originating cache, but the other two caches inconsistent since they still hold the old value.
- In a write-back policy, main memory not updated at the time of the store.
- Moreover, The copies in the other two caches and main memory Inconsistent.
- Memory updated eventually when the modified data in the cache copied back into memory.
- So, Another configuration that may cause consistency problems is a direct memory access (DMA) activity in conjunction with an IOP connected to the system bus.
- Also, In the case of input, the DMA may modify locations in main memory that also reside in a cache without updating the cache.
- During a DMA output, memory locations may read before they updated from the cache when using a write-back policy.