- When we are executing any instruction, we need the microprocessor to access the memory for reading instruction codes and the data stored in the memory.
- For this, both the memory and the microprocessor requires some signals to read/write to/from registers.
- The interfacing circuit, therefore, should be designed in such a way that it matches the memory signal requirements with the signals of the microprocessor.
Memory Read Cycle
It used to fetch one byte from the memory.
- Moreover, It requires 3 T-States.
- It can use to fetch operand or data from the memory.
- During T1, A8-A15 contains the higher byte of the address. At the same time ALE is high. Therefore Lower byte of address A0-A7 is selected from AD0-AD7.
- Since it is memory ready operation, IO/M ( bar) goes low.
- During T2 ALE goes low, RD (bar) goes low. The address is removed from AD0-AD7 and data D0-D7 appears on AD0-AD7.
- During T3, Data remains on AD0-AD7 till RD ( bar) is at low signal.
Memory Write Cycle
- It used to send one byte into memory.
- It requires 3 T-States.
- During T1, ALE is high and contains lower address A0-A7 from AD0-AD7.
- A8-A15 contains the higher byte of the address.
- As it is memory operation, IO/M ( bar) goes low.
- During T2, ALE goes low, WR (bar) goes low and Address removed from AD0-AD7 and then data appears on AD0-AD7.
- Data remains on AD0-AD7 till WR ( bar) is low.
How Control Signals Generated in 8085 Memory Interfacing
- The Memory Interfacing figure shows that four different control signals generated by combining the signals RD (bar), WR ( bar), and IO/M (bar ).
- The signal IO/M (bar) goes low for the memory operation. This signal ANDed with RD (bar) and WR (bar) signals busing the 74LS32 quadruple two-input OR gates, as shown in the figure.
- The OR gates functionally connected as negative NAND gates. When both input signals go low, the output of the gates go low and generate MEMR (bar) and MEMW (bar) control signals.
- When the IO/M (bar) signal goes high, it indicates the peripheral I/O operation.
- The figure shows that this signal complemented using the Hex inverter 74LS04 and ANDed with the RD ( bar) and WR (bar) signals to generate IOR (bar) and IOW (bar) control signals.