Multiport Memory Interconnection Structures
- A multiport memory system employs separate buses between each memory module and each CPU.
- This shown in figure 10.3 for four CPUs and four memory modules (MMs).
- Each processor bus connected to each memory module.
- A processor bus consists of the address, data, and control lines required to communicate with memory.
- The memory module said to have four ports and each port accommodates one of the buses.
- Also, The module must have internal control logic to determine which port will have access to memory at any given time.
- Moreover, Memory access conflict resolved by assigning fixed priorities to each memory port.
Figure: Multiport memory organization
- The priority for memory access associated with each processor may establish by the physical port position that its bus occupies in each module.
- So, Thus CPU 1 will have priority over CPU 2, CPU 2 will have priority over CPU 3. And CPU 4 will have the lowest priority.
- Moreover, The advantage of the multiport memory organization is the high transfer rate that can achieve because of the multiple paths between processors and memory.
- The disadvantage is that it requires expensive memory control logic and a large number of cables and connectors.