PROGRAMMABLE ARRAY LOGIC (PAL)
- Programmable array logic (a registered trademark of Monolithic Memories) is a particular family of programmable logic devices (PLDs) that is widely used and available from a number of manufacturers.
- The PAL circuits consist of a set of AND gates whose inputs can programme and whose outputs connected to an OR gate, i.e. the inputs to the OR gate hard-wired, i.e. PAL is a PLD with a fixed OR array and a programmable AND array.
The figure shows a small example of the basic structure. The fuse symbols represent fusible links that can burn open using equipment similar to a PROM programmer.
- The figure shows how the circuit programmed to implement F = A’BC + AB’C.
- So, All input variables and their complements left connected to the unused AND gate, whose output is, therefore, AA’BB’CC’ = 0. The 0 has no effect on the output of the OR gate.
- Moreover, The figure shows an example of how the PAL structure represented using the abbreviated connections. It is a 3-input 3-wide AND-OR structure.
- Also, Each function can have three minterms or product terms.
- Inputs to the OR gates at the outputs fixed as shown by ‘x’ marked on the vertical lines.
- Moreover, The inputs to the AND gates marked on the corresponding line by the ‘x’.
- Removing the ‘x’ implies blowing off the corresponding fuse which in turn implies that the corresponding input variable not applied to the particular AND gate.