Vectored & non-Vectored Interrupts
- In vectored interrupts, the processor automatically branches to the specific address in response to an interrupt.
- In vectored interrupts, the manufacturer fixes the address of the ISR to which the program control is to transfer.
- Also, The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
- TRAP the only non-maskable interrupt in the 8085.
- In non-vectored interrupts, the interrupted device should give the address of the interrupt service routine (ISR).
- Also, The INTR a non-vectored interrupt.
- Hence when a device interrupts through INTR, it has to supply the address of ISR after receiving interrupt acknowledge signal.
- The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and RST 7.
- Also, The software interrupts cannot be masked and they cannot be disabled.
- The vectored hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5.
- An external device initiates the hardware interrupts 8O85 by placing an appropriate signal at the interrupt pin of the processor.
- The processor keeps on checking the interrupt pins at the second T -state of last machine cycle of every instruction.
- Also, If the processor finds a valid interrupt signal and if the interrupt unmasked and enabled, then the processor accepts the interrupt.
- The acceptance of the interrupt acknowledged by sending an INTA signal to the interrupter device.
- Moreover, The processor saves the content of PC (Program Counter) in a stack and then loads the vector address of the interrupt in PC. (If the interrupt non-vectored, then the interrupting device has to supply the address of ISR when it receives INTA signal).
- It starts executing ISR at this address.
- At the end of ISR, a return instruction, RET will place.
- Also, When the processor executes the RET instruction, it POP the content on top of the stack PC.
- Thus the processor control returns to the main program after servicing interrupts.