Programmable Logic Array (PLA) & Xilinx FPGA
- The PLA combines the characteristics of the PROM and the PAL by providing both a programmable OR array and a programmable AND array, i.e. in a PLA both AND gates and OR gates have fuses at the inputs.
- The third set of fuses in the output inverters allows the output function to inverted if required. Usually, X-OR gates used for controlled inversion.
- However, it has some disadvantages. Because it has two sets of fuses, it is more difficult to manufacture, program and test it than a PROM or a PAL.
- The figure demonstrates the structure of a three-input, four-output PLA with every fusible link intact.
- Like ROM, PLA can be mask programmable or field programmable.
- With a mask programmable PLA, the user must submit a PLA programming table to the manufacturer.
- This table used by the vendor to produce a user made PLA that has the required internal paths between inputs and outputs.
- The second type of PLA available called a field programmable logic array or FPLA.
- The FPLA can programme by the user by means of certain recommended procedures. FPLAs can programme with commercially available programmer units.
The basic architecture is shown in the figure. The logic modules have inputs and outputs that can connect to metal lines by programmable switches.
- The direct lines allow signals to sent to or received from adjacent logic modules.
- Also, These direct lines can also programme to connect to the general purpose interconnect lines to allow interconnection of nonadjacent logic modules if required.
- In addition, signals can switch from one path to another at the intersections of rows and columns of the general purpose interconnect lines.
- Moreover, A simplified diagram of the configurable logic block or CLB shown in the figure.
- This block is similar to a two flip-flop, RAM -controlled state machine.